• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Junction field effect transistor and method of obtaining it. This document details both a binding field effect transistor device (JFET), object of a first aspect of the invention, and the method of obtaining it, object of a second aspect of the invention. The junction field effect transistor device (JFET) has a series of concentric circular trenches that are protected by one or more protective trenches. Said protection trenches are rectangular in shape with rounded corners and are unfolded in floating protection trenches and polarized protection trenches, such that a polarized protection trench is exterior to the last concentric trench while a floating protection trench is exterior to said polarized protection trench. (Machine-translation by Google Translate, not legally binding)
    公开号:ES2745740A1
    申请号:ES201830860
    申请日:2018-08-31
    公开日:2020-03-03
    发明作者:Comes Miguel Ullán；Fontanillo Carlos Couso；Villena Salvador Hidalgo；Gual David Flores；David Quirion
    申请人:Consejo Superior de Investigaciones Cientificas CSIC；
    IPC主号:
    专利说明:

    [0001] UNION FIELD EFFECT TRANSISTOR, METHOD OF OBTAINING AND
    [0002]
    [0003] OBJECT OF THE INVENTION
    [0004]
    [0005] The object of the invention is framed in the field of semiconductor devices and their manufacturing processes.
    [0006]
    [0007] More specifically, the object of the invention is aimed at a JFET type transistor device and a method for obtaining it.
    [0008]
    [0009] BACKGROUND OF THE INVENTION
    [0010]
    [0011] The JFET (English Junction Field-Effect Transistor, Spanish for junction field effect transistor) is a type of electronic device with three terminals S (source / Source), G (Gate / Gate) and D (drain / Drain), whose operation as an electronic switch is based on the electric field effect produced by the applied voltage difference between terminals S and G, VGS. According to this VGS input value, the output of the JFET type transistor will present a behavior that is simplified by defining two zones: active (on) and cut (off). The different IDS values based on the VGS are given by a graph or equation called the input equation.
    [0012]
    [0013] In the active zone, by allowing the passage of current, the transistor will give an output in the circuit that is defined by the drain current itself (IDS) and the voltage between the drain and the VDS source. The graph or equation that relates these two variables is called the output equation, and it is where the three operating zones are distinguished: ohmic, triode and saturation.
    [0014]
    [0015] Physically, a so-called "P-channel" JFET transistor is made up of a P-type semiconductor substrate, at the ends of which are two output terminals (drain and source) flanked by two N-type doping regions where connect the connected terminals together (gate). By applying a positive VGS voltage between gate and source, (PN junction) a carrier emptying area is created in the channel (region flanked by gate electrodes) reducing current flow between source and drain (IDS). When this VGS exceeds a certain value, the channel is completely empty of carriers and the IDS current between source and drain is negligible. This value of VGS is called shear stress (Voff). For a "N-channel" JFET the zones P and N are inverted, and the VGS and Voff are negative, cutting the current for voltages less than Voff (negative).
    [0016]
    [0017] These types of devices are known, along with those procedures for obtaining them. In this sense, various documents are known, such as US8068321B2, which details a conventional JFET for the overvoltage protection (protection against unwanted voltage spikes) of a low-voltage DC / DC converter. However, the device works as a Normally-off switch that only activates when it has to protect the main system by supporting unwanted current and where conduction is based on electrons and the technology is based on an initial N + substrate. over which a thin N "epitaxial layer is grown. Implants are then made to create the gate (boron) and the source (phosphor).
    [0018]
    [0019] Also, document US6251716B1 describes a JFET with low resistance and high switching speed in high current devices (100 A in large area chips). However, the tensile capacity is limited by the thickness of the epitaxial N layer. Furthermore, the aforementioned high switching speed cannot be achieved if a high voltage capacity is required and the conduction is based on electrons and the technology is based on an initial N + substrate, on which an N-epitaxial thin layer is grown. , to then create the multiple gates (boron) and the drain region (phosphor).
    [0020]
    [0021] Document US6380569B1 describes a conventional high-power, high-voltage JFET device, albeit in normal shutdown operation and based on conventional N + / N "substrates. In addition, a trench, including a gate oxide and the necessary filler material conductive, controls the JFET region. In fact, it features P-type diffusions at the bottom of the trench to prevent premature rupture. The device targets power applications where switching speed is not crucial but where a high current capacity.
    [0022]
    [0023] On the other hand, document US20090075435A1 has a device JFET that is based on the use of an insulating region created in the substrate, in an area close to its surface. This is essentially a SOI JFET and as a consequence the source, drain and gate electrodes have to be placed on the same side of the substrate, resulting in a low voltage. The process technologies described in US20090075435A1 are based on the insulation layer and differ from each other in how the top layer of semiconductors is created and doped. In all cases, a shallow trench is created and filled with polysilicon; the cross section of the JFET proposed in US20090075435A1 is based on electron currents and its topology is such that the JFET proposed in US20090075435A1 provides an extremely fast switching speed and low parasite level; that is, it is designed for high frequency and low voltage applications.
    [0024]
    [0025] In view of the above, the JFET devices found in the state of the art are widely used as switches or as a passive protection element. However, none of them is valid for high radiation applications, since for its manufacture it is necessary to use an interlevel oxide that fails under exposure of ionizing radiation. On the other hand, although the use of N-type substrates in electronic devices improves some of their electrical performance, it makes them more vulnerable to the effects of radiation, and therefore unable to operate in environments with a high presence of radiation. Thus, one of the relevant lines of research in modern power electronics is the search for appropriate devices for power distribution circuits and control systems that are capable of operating in high radiation environments.
    [0026]
    [0027] Document P201531371 details a vertical JFET device, in which the current flows from the top of the chip (source) to the bottom (drain), passing through the entire silicon block, as well as a method for the manufacture of said JFET device using DRIE ( Deep reactive-ion etching). This document describes a series of deep blind trenches in a block of P-type semiconductor material. These trenches are then filled with a layer of N-type conductive material, said trenches being preferably configured with a circular or polygonal section defining a body that encloses a volume of the P-type semiconductor block; that is, seen in plan, the polygon or circle defined on the surface of the block by the walls of the trench is made of a P-type material, while the trench must be filled with a conductive material of type N. The trench acts as gate of the transistor device, while the semiconductor part of the block enclosed between the walls of the trench (the mentioned circles or polygons seen in plan) will be the intrinsic active part of the JFET transistor, called channel. However, due to its design, the breakdown voltage in cut-off mode does not exceed 300 V. This voltage is too low for certain applications, where values of up to 1000 V are necessary for the proper functioning of the sensors. . The V-JFET voltage limitation (maximum breakdown voltage) is known to be intrinsic to its design, due to the small radius of curvature of the basic cell (<35 microns). The rupture occurs in the cells with the smallest radius, since when there is a voltage difference, the electric field rises rapidly in them until it reaches the breakage of silicon 3105 V / cm. This can be avoided by raising the radius of the basic cell, however, this radius cannot be simply increased, since some of the device's electrical performance such as: the cut-off voltage (Voff), the cutoff (Ioff) or saturation current (Isat). On the other hand, the current carrying capacity of each cell in the device described in P201531371 is quite limited (0.3 A / cm2), which implies having to make devices with excessively large areas (> 1 cm2) to be able to supply this deficiency , incompatible with conventional power packages for discrete devices.
    [0028]
    [0029] DESCRIPTION OF THE INVENTION
    [0030]
    [0031] In a first aspect of the invention there is a JFET device with multiple concentric rings, while in a second aspect of the invention there is a method for manufacturing the JFET device of the first aspect; method that preferably makes use of the DRIE ( Deep reactive-ion etching) processing technique .
    [0032]
    [0033] The transistor object of a first aspect of the invention presents a succession of concentric rings (multi-ring), where the distance between consecutive rings is small enough to keep intact the electrical characteristics of a JFET device and that the trench of each ring protect, against electrical breakdown, the adjacent inner ring. In this way, the only ring that must be protected against electrical breakdown will be the outermost ring of all of them, which can be designed with an arbitrarily large radius of curvature (depending only on the number of concentric rings included). The protection of the outer rings of each cell is done with three-dimensional elements, unlike the previous art (P201531371), where the termination of the V-JFET device is made only with 2D elements (guard rings and superficial implants) which demonstrate be insufficient for effective protection of the edge of the cell. The three-dimensional protection elements used in the present invention are called guard trenches, which may be polarized or floating depending on the requirements of the embodiment. The guard trench protection system can be implemented in the following way, a first protection ring or guard is polarized at the same voltage as the trenches of the MR-JFET devices, managing to generate a transition from the outer ring of the MR- JFET (with dimensions greater than 150 pm) to a polarized linear ring of infinite radius (straight line) and minimizing the probability of breakage. From this linear polarized ring, consecutive and parallel floating rings are generated, causing the electric field at the bottom of the trenches to decrease smoothly and progressively, as if they were 2D guard rings.
    [0034]
    [0035] Additionally, this transition just explained can be carried out more progressively, introducing more polarized rings between the transition of the outer ring until reaching the linear form.
    [0036]
    [0037] Another advantage of having concentric rings is that deep trenches can be engraved while maintaining mechanical stability, since in no case do these trenches coincide with the crystallographic planes of silicon.
    [0038] Therefore, the use of the "multi-ring" arrangement provides great advantages over the prior art, for example:
    [0039] • The evident increase in the radius of curvature of the outer ring, which increases the breaking voltage of the device.
    [0040] • Since the cells can be designed in different sizes, by varying the number of rings, more area of the silicon can be used. This increases the current capacity of the device. Also, a cell (several concentric rings) or several cells (several concentric ring groups) can be arranged within the same protection trenches.
    [0041] • The source contacts , which are placed in the center between each two consecutive rings (channels), have a greater area and therefore increases the injection of electrons into the channel, increasing its current capacity.
    [0042]
    [0043] The transistor of the object of the invention can operate as a resistance of the size of the intrinsic conduction volume (channel or channels) in those situations where it is in the linear region, this resistance can be close to zero at low input voltages or low source-drain bias. In these situations it proceeds to increase the source-drain polarization in such a way that an increase in voltage occurs in the channel. The bottom of the channel empties progressively until a "choke" voltage is reached where the bottom of the channel is completely emptied and the current becomes saturated. On the other hand, if the gate voltage is increased, inverting the PN junction formed with the internal semiconductor and the gate of the device, the channel is increasingly depleted, until it is completely empty at a value of V0tr in particular, and consequently there is no current conduction in the channel.
    [0044]
    [0045] In an embodiment of the first aspect of the invention, the channel of the transistor object of the invention is made of P-type silicon, and the trenches are filled with an N-type material such as polysilicon, which can be highly doped. In this way, the device can be used as a radiation resistant power switch in power distribution applications. P-type silicon is not reversed (at N-type) due to the displacement damage of non-ionizing radiation, making the substrate more resistant to this type of radiation. Furthermore, the only oxides present in the device are on its surface, which makes the device more robust against ionizing radiation damage due to its vertical configuration. Additionally, the radius of the intrinsic channel can be reduced until obtaining a low cut-off voltage that allows the use of a low-power control circuit made with a CMOS sub-micron (DSM) CMOS process, which makes the complete system even more resistant to radiation, since DSM processes are inherently more resistant to radiation. In this way, the device can be used as a power switch in power distribution applications in environments subject to high radiation.
    [0046]
    [0047] Among the possible uses of the transistor of the invention or obtainable by the method of the second aspect of the invention is the use as a switch or as a radhard switch (the so-called switch or rad-hard switch). Also, it could be used as a current limiter normally-on.
    [0048]
    [0049] DESCRIPTION OF THE DRAWINGS
    [0050]
    [0051] To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, in accordance with a preferred example of practical embodiment thereof, it is included as an integral part of Said description, a set of drawings in which, by way of illustration and not limitation, the following has been represented:
    [0052]
    [0053] Figures 1-5: Show respective plan views and (cross sections) marked by broken lines showing the manufacture of a preferred embodiment of the object of the invention.
    [0054]
    [0055] PREFERRED EMBODIMENT OF THE INVENTION
    [0056]
    [0057] In an embodiment of the invention, the second aspect thereof related to the method of obtaining the JFET transistor device, also referred to throughout this example as a device or simply a transistor, has the first aspect of the invention started , in a preferred embodiment of the invention described here (Figures 1-5).
    [0058] In this way, it is had that the second aspect of the invention related to the method of obtaining the JFET transistor of the first aspect of the invention is started, as observed in figure 1. The starting material for the embodiment is a P type semiconductor block (1) preferably, an alternative embodiment can be made with an N type semiconductor, conveniently changing the rest of doping. From this block (1), a growth of a first layer of dielectric (2), such as silicon oxide, is made by thermal processes to passivate the Si surface.
    [0059]
    [0060] Next, a pattern is made on the first dielectric layer (2) together with a selective implantation of N-type dopant elements (3) when the block (1) is of a P-type semiconductor and vice versa with P-type dopants when the The semiconductor of the block (1) is type N, to subsequently proceed to a thermal process to conform the result shown in figure 2. Note that the different colors of the filling of the plan view of figure 2 represent the pattern of the implantation performed.
    [0061]
    [0062] Next, a metal layer is deposited which, once defined according to the corresponding pattern, will act as a selective mask for the subsequent deep engraving of silicon. In this way circular concentric crowns are created (blind trenches less than 5 microns wide) that will serve as door contacts (4), made in the first dielectric layer (2) and that reaches the interior of the block (1) of semiconductor material, to a depth of around 80 microns, as seen in figure 3. The difference between the smallest radius of a crown and the largest radius of the crown immediately preceding it is constant throughout the series of crowns, in such a way that successive concentric channels (6) with a circular crown shape of semiconductor material of the block (1) are defined in the space between the concentric circular trenches (4).
    [0063]
    [0064] Additionally, in the same deep silicon engraving process, protection trenches (51, 61) are made, the number of which depends on the necessary protection of the particular embodiment, but always at least one of each, which also they are less than 5 microns in width, made in the first dielectric layer (2) and reaching the interior of the block (1) of semiconductor material, to a depth of around 80 microns. These protection trenches (51, 61), preferably with a rectangular or square shaped plant and preferably with rounded corners, around the outermost circular trench (4), at a distance of the order of 20 microns, will serve as guard trenches for the edge of the device. In the preferred embodiment of the second aspect of the invention, the trench (4) immediately external to the last trench (4) of the cell is polarized at the same voltage as the door (5). While the subsequent trench (4) remains floating, contributing to a rise in the breakdown voltage by smoothing the electric field in the device.
    [0065]
    [0066] Later the metal that has served as a mask is engraved, removing it completely. Alternatively, a different material, such as silicon oxide, can be used to mask the deep engraving.
    [0067]
    [0068] In a preferred embodiment shown in Figure 4, the trench (4) made in the block (1) is filled with conductive doped polysilicon (41) whose doping is type P or N as necessary depending on the type of semiconductor of the block (1) being the doping of the opposite type to that of the semiconductor of the block (1). Subsequently, a thermal process is carried out to extend the P or N type dopants from the doped polysilicon to the trench walls, thus defining the different gate contacts (41) of the JFET type transistor of the invention.
    [0069] In this same trench filling process and subsequent thermal process, the first and second guard rings defined by the protection trenches (51, 61) corresponding to a polarized protection trench (51) and a floating trench of protection (61), in such a way that there is at least one polarized protection trench (51) made in the dielectric layer (2) and that reaches inside the block (1) of semiconductor material and outside the concentric series of trenches (4) and at least one floating protection trench (61) made in the dielectric layer (2) and reaching the interior of the block (1) of semiconductor material and outside the polarized protection trench (51) and preferably at least partially coincident with the edge of the transistor.
    [0070]
    [0071] Subsequently, a selective engraving process of the first dielectric layer (2) is carried out in a specific area in the center of the channels (6), to perform a selective implantation of D or N type doping elements as necessary , of the same type as the semiconductor of the block (1), only in the areas where the first dielectric layer (2), that is to say the silicon oxide, has been engraved, to subsequently proceed to a thermal process to conform the result that is seen in figure 4, defining the source contacts (71) of the transistor.
    [0072]
    [0073] Next, a selective implementation process of P or N doping elements is carried out as necessary, of the same type as the semiconductor of block (1), on the back of block (1) to subsequently proceed to a thermal process to conform the result that can be seen in figure 4, defining the drain contacts (72) of the transistor.
    [0074]
    [0075] Subsequently, a growth or, alternatively, a second dielectric layer (8), which can be silicon oxide, is carried out by means of thermal processes to act as an insulating layer between conductive layers. Subsequently, a selective engraving of this second layer of dielectric (8) is made in specific areas for the opening of respective contact windows (91, 101) for the door (4) and the protection trench (51) and for the source (10) of the transistor, as seen in figure 5.
    [0076]
    [0077] Alternatively, in those embodiments in which the block (1) is N-type semiconductor, the doping of the conductor (41) that defines the door (4), will be of type P and, in turn, that of the elements that define the drain (72) and the source (71), must be type N.
    [0078]
    [0079] Next, a first layer of conductive material (9) is deposited on the surface as seen in the plan view of figure 5, which contacts the door (4) and a first guard ring defined by the polarized protection trench. (5) through the contact window (91) that reveals the implant (3).
    [0080]
    [0081] Next, a second layer of conductive material (10) that covers the cell is deposited together with all the channels (6) as seen in the elevation of figure 5, which contacts all the source contacts (71), through of the windows of the source contacts (101) that expose the implants, as seen in the section OB of figure 5
    [0082]
    [0083] Finally, a third layer of low resistivity electrical conductive material (721) is deposited, which covers the entire surface at its bottom, on the back of the block (1) as seen in section AO and BO of Figure 5, which defines the drain contact (721) of the device.
    权利要求:
    Claims (11)
    [1]
    1. - JFET type transistor comprising a block (1) of semiconductor material uniformly doped type P or N or with a highly doped epitaxial layer, the JFET type transistor being characterized in that it comprises:
    - a first dielectric layer (2) that covers at least partially a surface of the block (1),
    - at least a series of concentric circular trenches (4) made in the dielectric layer (2) and reaching into the block (1) of semiconductor material defining between them a series of channels (6) of block semiconductor material (1) where the internal wall of the trench (4) comprises a doped semiconductor material of the opposite type to that of the semiconductor material of the block (1), thus defining the gate (4) of the JFET type transistor,
    - at least one polarized protection trench (51) made in the dielectric layer (2) and that reaches inside the block (1) of semiconductor material and is external to the series or series of concentric trenches (4),
    - at least one floating protection trench (61) made in the dielectric layer (2) and reaching inside the block (1) of semiconductor material and outside the polarized protection trench (51),
    - a second dielectric layer (8) that covers at least partially the surface of the block (1) and the first dielectric layer (2),
    - a first layer of low resistivity electrically conductive material (9) that covers at least partially the door (5), and contacts the door (5) defining a door contact (81), and with the polarized trench (61),
    - a second layer of electrically conductive material with low resistivity (10) that covers at least partially the channels (6) at their upper part defining a source contact (71), and
    - a third layer of electrically conductive material with low resistivity (72) that covers at least partially the channel (6) by its lower part defining a drain contact (721).
    [2]
    2. - JFET type transistor according to claim 1 characterized in that the trenches (4) have a section of several concentric circular crowns.
    [3]
    3. - JFET type transistor according to claim 1 or 2, characterized in that the trenches (4) have a depth less than the thickness of the block (1).
    [4]
    4. - JFET type transistor according to any of embodiments 1 to 3 characterized in that the channel is made of silicon, and the trenches (41) are filled with polysilicon.
    [5]
    5. - JFET type transistor according to any of embodiments 1 to 4 characterized by the addition of circular or polygonal polarized protection crowns (51) around the circular crowns that form the JFET cell (4).
    [6]
    6. - JFET type transistor according to any of embodiments 1 to 5 characterized by the addition of floating circular or polygonal protection crowns (61) around the circular crowns that form the JFET cell (4) or the polarized crowns (51 )
    [7]
    7. - JFET type transistor according to claim 1 characterized in that the dielectric layer (8) is made of a material that is selected from silicon dioxide and silicon nitride.
    [8]
    8. - Method for obtaining a JFET transistor, a method characterized in that it comprises:
    i. growing a first layer of dielectric (2) on a surface of the block (1), i. stamp the first layer of dielectric (2),
    ii. doping at least a zone of the surface of the block (1) through the first dielectric layer (2) with dopants (3) of the opposite type to that of the block (1), iv. applying an annealing heat treatment to the result of the previous step, v. make a series of blind holes:
    - in the form of a crown on the first dielectric layer (2), which reach an interior area of the block (1) and define concentric trenches (4),
    - with a rectangular or square shape with rounded corners, which reach an interior area of the block (1) and define one or more polarized protection trenches (51) and one or more floating protection trenches (62) where the polarized protection trench (51) is outside the trenches (4) and the floating protection trench (61) is outside the polarized protection trench (51),
    saw. carry out a thermal process to extend the N-type dopants from the doped polysilicon to the walls of the trenches (4), thus defining the gates (41) of the transistor,
    vii. practice at least selective etching on the first dielectric layer (2) defining a window that exposes the surface of the block (1) in the center of each channel (6), to perform a selective implementation of doping elements only in the areas where the silicon oxide has been recorded, to subsequently proceed to a thermal process, defining a source (71),
    viii. carry out a selective implementation process of doping elements on the back of the block (1) to subsequently proceed to a thermal process defining the drain (721) of the device,
    ix. depositing a second layer of dielectric (8) to act as an insulating layer between conductive layers, and performing a selective engraving of said second layer of dielectric (8) in specific areas for opening windows (91,101) of contact to the door (41) and polarized trench (51) and to the source (92),
    x. depositing a first layer of conductive material (9), which contacts the gate (41) of the transistor,
    xi. selectively etching the conductive material layer (10) in specific areas to define a source contact (10) of the transistor, and
    xii. depositing a third layer of low resistivity electrical conductive material (721) that covers at least partially the channel (6) by its lower part on the back of the block (1), which contacts the drain (72) of the device and defines the contact of drain (721) of the device.
    [9]
    9. - Method according to claim 8 characterized in that the trench (4) has a thickness not greater than 5 microns.
    [10]
    10. - Method according to claim 8 characterized in that the trench (4) has a depth of between 60 and 100 microns.
    [11]
    11. - Use of the JFET type transistor described in any one of claims 1 to 7 or obtainable by the method described in any one of claims 8 to 2 as a switch or as a current limiter.
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    同族专利:
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
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    US6380569B1|1999-08-10|2002-04-30|Rockwell Science Center, Llc|High power unipolar FET switch|
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    PCT/ES2019/070578| WO2020043927A1|2018-08-31|2019-08-29|Junction field-effect transistor, method for obtaining same and use thereof|
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